The present invention relates to a semiconductor integrated circuit, and, more particularly, to an input buffer of a semiconductor integrated circuit capable of performing various operation modes on-chip.
Generally, in existing semiconductor integrated circuits, various operation modes are installed within on-chip in order to freely perform specific operation modes, at the request of a user. With such circuits, input pads identical to each other are moved according to an arrangement of a pin for performing respective operation mode so that a plurality of input pads used in the respective operation mode are provided and wire-bonded in accordance with arrangement of the pin.
When the various operation modes are installed within a single chip in a prior art input buffer, several input pads corresponding to the operation modes are required. As a result, the size of chip is enlarged in proportion to the increased number of input pads, which decreases the number of net die. This results in a problem that the product manufacturing efficiency is lowered. To solve this problem, however, the optional-connection of a fuse between a single input pad and an input pad adjacent thereto and by an adaptive usage of the single input pad to the pin corresponding to the operation mode has been proposed so that a problem caused due to arrangement of pins can be removed without increasing the number of input pads.
FIG. 1 is a circuit diagram illustrating a conventional input buffer. An input buffer of FIG. 1 is composed of an NMOS transistor 2, a first fuse f1, a second fuse f2, a third fuse f3 and an NMOS transmission transistor TG. The NMOS transistor 2 is connected between a power supply voltage Vcc and a control node N, and to a control voltage V1 at its gate terminal. The first fuse f1 is connected between the control node N and ground voltage terminal, the second fuse f2 between a first input pad and a first TTL buffer (transistor--transistor logic buffer), and the third fuse f3 between a second input pad and a second TTL buffer. The NMOS transmission transistor TG is connected between the first input pad and the second fuse f2 at its drain terminal, and to the control node N at its gate terminal, and between the third fuse f3 and the second TTL buffer at its source terminal.
In the input buffer shown in FIG. 1, a state of the control node N, which controls the gate terminal of NMOS transmission transistor TG, depends on a state of the first fuse f1. When the level of control voltage V1 rises to a fully logic "high" state, if the first fuse f1 is cut off, the NMOS transistor 2 is turned ON to thereby turn ON the NMOS transmission transistor TG, and thus an output of the first input pad is transmitted to the first TTL buffer or/and the second TTL buffer according to the states of the second and third fuses f2 and f3. If the first fuse f1 is not cut off, the NMOS transmission transistor TG is turned OFF. Thus, the output of the first input pad is supplied as an input of the first TTL buffer and an output of the second input pad is supplied as an input of the second TTL buffer.
On the other hand, if the outputs of the first and second input pads have a level of -2 V or so, respectively, a gate-source voltage Vgs of the NMOS transmission transistor TG becomes increased, thereby causing the NMOS transmission transistor TG to be changed from turned-off state to a turned-on state. In this case, a cross-talk between the first input pad and the second input pad is generated, such that the first and the second TTL buffers operate incorrectly.
As shown in FIG. 1, the transmission gate has been used for modifying paths of the input pads and the TTL buffer, but in this case, a noise is generated due to the cross-talking between input pads according to an on/off operation of the transmission gate, and therefore unexpected malfunction of the chip may occur.